报 告 人：Sybille Hellebrand 教授
Sybille Hellebrand has a Diploma degree in Mathematics from the University of Regensburg, Germany, and a PhD degree in Computer Science from the University of Karlsruhe, Germany. Then she was as a postdoctoral fellow at the TIMA/IMAG-Computer Architecture Group, Grenoble, France, and continued as a research and teaching assistant at the University of Siegen, Germany. Before completing her “Habilitation” and changing to the Division of Computer Architecture at the University of Stuttgart, Germany, in 1997, she spent several months as a guest researcher with Mentor Graphics Corporation in Portland, Oregon, USA. In 1999 she moved to the University of Innsbruck in Austria as a full professor for Computer Science. During her time in Innsbruck she was the head of the Institute of Computer Science from 2001 to 2004. Since 2004, she has a chair in Computer Engineering at the University of Paderborn, Germany. From 2006 to 2011 she was also the head of the Institute of Electrical Engineering and Information Technology. In 2014 she was appointed guest professor at Hefei University of Technology in China.
Her main research interests include test and diagnosis of micro-electronic systems, in particular built-in test, built-in diagnosis and built-in repair for systems-on-a-chip, as well as design and synthesis of testable and dependable circuits and systems. She has published numerous papers in international conferences, workshops, and journals. Besides her activities in several program committees, she serves as an associate editor of the Journal of Electronic Testing - Theory and Applications (JETTA). From 2002 to 2009 she was a member of the editorial board of IEEE Transactions on Computer-Aided Design of Circuits and Systems.
Week devices often remain undetected during manufacturing test, as they do not change the circuit outputs. However, further degradation may turn them into hard defects causing early life failures, which are often associated with costly product recalls and high economic losses. The prediction of early life failures during manufacturing test or by low-cost tests in the field is thus a reseach goal of paramount importance.
Small delay faults have been identified as indicators for week devices, but they may be undetectable even by the most advanced procedures for automatic test pattern generation (ATPG). This presentation focuses on the opportunities and challenges of targeting such hidden delay faults by faster-than-at-speed test (FAST). In particular, techniques for efficient frequency selection and DFT measures for a built-in FAST will be presented.